This invention relates generally to the fabrication of integrated circuits.
When making a complementary metal oxide semiconductor (CMOS) device that includes metal gate electrodes, it may be necessary to make the NMOS and PMOS gate electrodes from different materials. A replacement gate process may be used to form gate electrodes from different metals. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed to create a trench between the spacers. The trench is filled with a first metal. The second polysilicon layer is then removed, and replaced with a second metal that differs from the first metal.
The first and second polysilicon layers may be formed on a dielectric layer. The dielectric layer serves as an etch stop layer and prevents significant numbers of ions from reaching the channel, when ions are implanted into the polysilicon layers. The dielectric layer may, for example, comprise silicon dioxide or, alternatively, a high-k dielectric layer.
To enable the first polysilicon layer to be removed without removing a significant amount of the second polysilicon layer, it may be desirable to dope the second polysilicon layer with p-type impurities. If an ion implantation process is used to dope that layer, ions may penetrate through an underlying silicon dioxide layer—if that layer is too thin. In addition, if the polysilicon layers are removed using a wet etch process, a silicon dioxide layer that is too thin may not prevent the etchant from attacking the underlying substrate. For these reasons, if the first and second polysilicon layers are formed on an ultra thin silicon dioxide layer, process steps for removing those polysilicon layers may damage the channel region.
Replacing an ultra thin silicon dioxide layer with a high dielectric constant (high-k) dielectric layer may prevent such process steps from damaging the channel region. It may, however, be difficult to accurately pattern a high-k dielectric layer. In addition, etching a high-k dielectric layer will expose surfaces of that layer. Those exposed surfaces may leave the channel region vulnerable to oxidation.
The metal gate field effect transistor may have a horizontal gate dielectric between the metal gate and the substrate. Such a transistor may also have a vertical portion of the gate dielectric that extends upwardly along the sides of the metal gate.
The vertical portion of the gate dielectric may increase fringe capacitance at the gate sidewalls. This fringe capacitance reduces the speed of the resulting electronic devices.
Thus, there is a need for a way to reduce the fringe capacitance arising from vertical gate dielectric portions in metal gate field effect transistors.
Features shown in these figures are not intended to be drawn to scale.